1. Technical Field
The present invention relates to multiple layer integrated circuit fabrication, and more particularly to a method for forming a subminimum size feature on a structure having a minimum or subminimum width.
2. Background Art
In integrated circuit fabrication of multiple layer structures it is frequently required that a second structure be formed on a first structure without the edge of the second structure extending beyond the edge of the first structure. Also, it may be required that the first structure have a width which is the minimum or subminimum size defined by the lithography employed in the fabrication.
For example, in forming a contact opening such as a via between two wiring levels as shown in FIG. 1 it is important that the subminimum via opening 10 in the dielectric layer 12 does not overlap the edge of an underlying conductor 14.
Another example is the formation of a contact 16 to a diffusion 18 disposed between two gate conductors 20a and 20b as shown in FIG. 2 wherein it is important that the contact 16 does not short to either gate conductor 20a or 20b. This would eliminate the need for a robust etch barrier when forming a borderless contact to a diffusion.
A third example as shown in FIG. 3 is the case wherein it is desirable to minimize the depth of a Shallow Trench Isolation (STI) 22 within a substrate 24 in order to reduce the aspect ratio of the trench and facilitate filling the trench with an insulating material.
Problems occur in the prior art fabrication techniques of FIG. 3. The presence of the full isolation implant through the implant window in photoresist layer 28 into the active device area such as area 26a requires the STI 22 be made deeper to prevent interaction with the devices. This happen when the isolation implant window misaligns with the STI, which occurs on a random basis. Since the isolation implant peak needs to be approximately at the bottom of the STI, deep STI moves the relatively high isolation doping concentration away from the surface of the device. Also, when the field implants are done prior to STI filling while the pad nitride layer covers the active areas 26a and 26b, then the filled implant self aligns with the STI 22. Subsequent high temperature steps will significantly diffuse any implant aligned to the STI region into the active device regions producing increased sensitivity, increased junction capacitance and enhanced fields within the silicon. Furthermore, the substrate hot carrier effect becomes a significant design constraint when minimum isolation depth is desired.
An example of a prior art technique is disclosed in the publication "Doping Profile Design For Substrate Hot Carrier Reliability In Deep Submicron Field Effect Transistors," Tonti et al., 29'th Annual International Reliability Physics Symposium.
The present invention uses what is referred to as a dual tone or hybrid photoresist. Dual tone or hybrid photoresists and their application are disclosed in co-pending U.S. patent applications Ser. No. 08/715,287, filed Sep. 16, 1996, entitled FREQUENCY DOUBLING HYBRID PHOTORESIST; Ser. No. 08/715,288, filed Sep. 16, 1996, entitled LOW "K" FACTOR HYBRID PHOTORESIST; and Ser. No. 08/851,973, filed May 7, 1997, entitled ESD PROTECTION STRUCTURE AND METHOD.